Silicon precursor, method of forming a layer using the same, and method of fabricating semiconductor device using the same

ABSTRACT

The inventive concepts provide silicon precursors, methods of forming a layer using the same, and methods of fabricating a semiconductor device using the same. The silicon precursor includes a silane group including two or more silicon atoms. The silicon precursor has a high and uniform adsorption property on surfaces of layers (e.g., a silicon layer, an oxide layer, and a nitride layer) that are mainly used when semiconductor devices are fabricated.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2014-0045575 filed on Apr. 16, 2014, the disclosureof which is hereby incorporated herein by reference in its entirety.

BACKGROUND

The inventive concepts relate to silicon precursors, methods of forminga layer using the same, and methods of fabricating a semiconductordevice using the same.

As semiconductor devices have been highly integrated, widths and spacesof semiconductor patterns have been reduced. Recently, three-dimensional(3D) semiconductor devices including vertically stacked patterns havebeen developed to improve an integration degree of semiconductordevices, so aspect ratios of recessed regions (e.g., contact holes ortrenches) have been increased in the 3D semiconductor devices. Thus, itmay be difficult to uniformly and conformally form a layer in therecessed regions having the high aspect ratio.

SUMMARY

Embodiments of the inventive concepts may provide silicon precursorscapable of providing an excellent seed property.

Embodiments of the inventive concepts may also provide methods offorming a layer having an improved step coverage property.

Embodiments of the inventive concepts may also provide methods offabricating a semiconductor device capable of improving reliability.

In one aspect, a silicon precursor includes a chemical formula ofR¹—Si_(x)H_(y). In the chemical formula of R¹—Si_(x)H_(y), “x” is anintegral number equal to or greater than 2, “y” satisfies an equationy=2x+1, and “R¹” includes at least one of an amino group, an alkylgroup, a cyclopentadienyl (C₅H₅) group, or a halogen.

In some embodiments, the “R¹” may be the amino group and has thefollowing chemical formula 1.

-   -   where each of “R²” and “R³” includes at least one of a methyl        group, an ethyl group, a propyl group, an isopropyl group, or a        butyl group.

In some embodiments, “Si_(x)H_(y)” may have a linear structure or abranched structure.

In another aspect, a method of forming a layer may include: providingthe silicon precursor of chemical formula of R¹—Si_(x)H_(y) on asubstrate to form a single-layered silicon atomic layer. In the chemicalformula of R¹—Si_(x)H_(y), “x” is an integral number equal to or greaterthan 2, “y” satisfies an equation y=2x+1, and “R¹” includes at least oneof an amino group, an alkyl group, a cyclopentadienyl (C₅H₅) group, or ahalogen.

In some embodiments, the method may further include: forming a siliconnitride layer, a silicon oxide layer, or a silicon-germanium layer onthe silicon atomic layer.

In some embodiments, the method may further include: forming apoly-silicon layer on the silicon atomic layer by providing at least oneof monosilane (SiH₄), disilane (Si₂H₆), or a high-grade silane(Si_(n)H_(2n+2), where “n” is an integral number equal to or greaterthan 3).

In some embodiments, forming the poly-silicon layer may further include:doping the poly-silicon layer by providing at least one of Group IIIelements, Group V elements, or carbon.

In some embodiments, the method may further include: forming anon-silicon atomic layer on the silicon atomic layer. Forming thesilicon atomic layer and forming the non-silicon atomic layer may bealternately and repeatedly performed, and the non-silicon atomic layermay be formed by providing a gas including oxygen, nitrogen, orgermanium.

In some embodiments, the “R¹” may be the amino group and has thefollowing chemical formula 1.

where each of “R²” and “R³” independently includes at least one of amethyl group, an ethyl group, a propyl group, an isopropyl group, abutyl group, or a tert-butyl group.

In some embodiments, the silicon precursor may bediisopropylaminodisilane (((CH₃)₂CH)₂N—SiH₂SiH₃).

In some embodiments, the substrate may include an oxide layer formedthereon, and the silicon precursor may be provided on the oxide layer.

In still another aspect, a method of fabricating a semiconductor devicemay include: providing the silicon precursor of chemical formula ofR¹—Si_(x)H_(y) on a substrate to form a single-layered silicon atomiclayer. In the chemical formula of R¹—Si_(x)H_(y), “x” is an integralnumber equal to or greater than 2, “y” satisfies an equation y=2x+1, and“R¹” includes at least one of an amino group, an alkyl group, acyclopentadienyl (C₅H₅) group, or a halogen.

In some embodiments, the method may further include: forming a lowerstructure including a recessed region on the substrate before theformation of the silicon atomic layer. The silicon atomic layer may beformed to conformally cover the lower structure.

In some embodiments, the recessed region may be a contact hole. In thiscase, forming the lower structure may include: forming an interlayerinsulating layer covering the substrate; and patterning the interlayerinsulating layer to form the contact hole.

In some embodiments, the method may further include: forming apoly-silicon layer filling the contact hole on the silicon atomic layerby providing at least one of monosilane (SiH₄), disilane (Si₂H₆), or ahigh-grade silane (Si_(n)H_(2n+2), where “n” is an integral number equalto or greater than 3) after the formation of the silicon atomic layer.

In some embodiments, the method may further include: forming a contactplug including a portion of the poly-silicon layer in the contact hole;and forming a data storage element electrically connected to the contactplug. For example, the data storage element may be a capacitor.

In some embodiments, the recessed region may be an active hole. In thiscase, forming the lower structure may include: alternately andrepeatedly stacking sacrificial layers and inter-gate insulating layerson the substrate; and successively patterning the inter-gate insulatinglayers and the sacrificial layers to form the active hole exposing thesubstrate.

In some embodiments, the method may further include: forming an activepillar covering a sidewall of the active hole after the formation of thesilicon atomic layer, the active pillar having a cup-shape; andreplacing the sacrificial layers with a conductive layer.

In some embodiments, forming the active pillar may include: conformallyforming a poly-silicon layer on the silicon atomic layer by providing atleast one of monosilane (SiH₄), disilane (Si₂H₆), or a high-grade silane(Si_(n)H_(2n+2), where “n” is an integral number equal to or greaterthan 3). The poly-silicon layer may cover the sidewall of the activehole.

In some embodiments, the “R¹” may be the amino group and has thefollowing chemical formula 1.

where each of “R²” and “R³” independently includes at least one of amethyl group, an ethyl group, a propyl group, an isopropyl group, abutyl group, or a tert-butyl group.

In some embodiments, the silicon precursor may bediisopropylaminodisilane (((CH₃)₂CH)₂N—SiH₂SiH₃).

In some embodiments, the substrate may include an oxide layer formedthereon, and the silicon precursor may be provided on the oxide layer

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concepts will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIGS. 1A and 1B are cross-sectional views illustrating adsorptionprocesses of a silicon precursor according to some embodiments of theinventive concepts;

FIGS. 2A, 2B, and 2C are cross-sectional views illustrating methods offorming a layer according to some embodiments of the inventive concepts;

FIG. 3 is a graph illustrating the result of a first experimentalexample;

FIG. 4 is a graph illustrating the result of a second experimentalexample;

FIGS. 5 to 11 are perspective views illustrating a method of fabricatinga semiconductor device according to some embodiments of the inventiveconcepts;

FIG. 12 is a plan view illustrating a semiconductor device according toother embodiments of the inventive concepts;

FIGS. 13 to 17 are cross-sectional views taken along a line A-A′ of FIG.12 to illustrate a method of fabricating the semiconductor device ofFIG. 12;

FIG. 18 is a schematic block diagram illustrating an electronic deviceincluding a semiconductor device according to embodiments of theinventive concepts; and

FIG. 19 is a schematic block diagram illustrating a memory systemincluding a semiconductor device according to embodiments of theinventive concepts.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the inventive concepts are shown. The advantages and features of theinventive concepts and methods of achieving them will be apparent fromthe following exemplary embodiments that will be described in moredetail with reference to the accompanying drawings. It should be noted,however, that the inventive concepts are not limited to the followingexemplary embodiments, and may be implemented in various forms.Accordingly, the exemplary embodiments are provided only to disclose theinventive concepts and let those skilled in the art know the category ofthe inventive concepts. In the drawings, embodiments of the inventiveconcepts are not limited to the specific examples provided herein andare exaggerated for clarity.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the invention. As usedherein, the singular terms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items. It will beunderstood that when an element is referred to as being “connected” or“coupled” to another element, it may be directly connected or coupled tothe other element or intervening elements may be present.

Similarly, it will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may be present.In contrast, the term “directly” means that there are no interveningelements. It will be further understood that the terms “comprises”,“comprising,”, “includes” and/or “including”, when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Additionally, the embodiment in the detailed description will bedescribed with sectional views as ideal exemplary views of the inventiveconcepts. Accordingly, shapes of the exemplary views may be modifiedaccording to manufacturing techniques and/or allowable errors.Therefore, the embodiments of the inventive concepts are not limited tothe specific shape illustrated in the exemplary views, but may includeother shapes that may be created according to manufacturing processes.Areas exemplified in the drawings have general properties, and are usedto illustrate specific shapes of elements. Thus, this should not beconstrued as limited to the scope of the inventive concepts.

It will be also understood that although the terms first, second, thirdetc. may be used herein to describe various elements, these elementsshould not be limited by these terms. These terms are only used todistinguish one element from another element. Thus, a first element insome embodiments could be termed a second element in other embodimentswithout departing from the teachings of the present invention. Exemplaryembodiments of aspects of the present inventive concepts explained andillustrated herein include their complementary counterparts. The samereference numerals or the same reference designators denote the sameelements throughout the specification.

Moreover, exemplary embodiments are described herein with reference tocross-sectional illustrations and/or plane illustrations that areidealized exemplary illustrations. Accordingly, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, exemplaryembodiments should not be construed as limited to the shapes of regionsillustrated herein but are to include deviations in shapes that result,for example, from manufacturing. For example, an etching regionillustrated as a rectangle will, typically, have rounded or curvedfeatures. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope ofexample embodiments.

As appreciated by the present inventive entity, devices and methods offorming devices according to various embodiments described herein may beembodied in microelectronic devices such as integrated circuits, whereina plurality of devices according to various embodiments described hereinare integrated in the same microelectronic device. Accordingly, thecross-sectional view(s) illustrated herein may be replicated in twodifferent directions, which need not be orthogonal, in themicroelectronic device. Thus, a plan view of the microelectronic devicethat embodies devices according to various embodiments described hereinmay include a plurality of the devices in an array and/or in atwo-dimensional pattern that is based on the functionality of themicroelectronic device,

The devices according to various embodiments described herein may beinterspersed among other devices depending on the functionality of themicroelectronic device. Moreover, microelectronic devices according tovarious embodiments described herein may be replicated in a thirddirection that may be orthogonal to the two different directions, toprovide three-dimensional integrated circuits.

Accordingly, the cross-sectional view(s) illustrated herein providesupport for a plurality of devices according to various embodimentsdescribed herein that extend along two different directions in a planview and/or in three different directions in a perspective view. Forexample, when a single active region is illustrated in a cross-sectionalview of a device/structure, the device/structure may include a pluralityof active regions and transistor structures (or memory cell structures,gate structures, etc., as appropriate to the case) thereon, as would beillustrated by a plan view of the device/structure.

A silicon precursor according to the inventive concepts has a chemicalformula of R¹—Si_(x)H_(y), where “x” is an integral number equal to orgreater than 2, “y” satisfies an equation y=2x+1, and “R¹” includes atleast one of an amino group, an alkyl group, a cyclopentadienyl (C₅H₅)group, or a halogen.

In some embodiments, “R¹” may be the amino group and may have astructure expressed by the following chemical formula 1.

where each of “R²” and “R³” includes at least one of a methyl group, anethyl group, a propyl group, an isopropyl group, or a butyl group.

“Si_(x)H_(y)” may have a linear structure or a branched structure.

Next, a method of forming a layer using the silicon precursor of theinventive concepts will be described. FIGS. 1A and 1B arecross-sectional views illustrating adsorption processes of a siliconprecursor according to some embodiments of the inventive concepts.

Referring to FIG. 1A, a substrate 1 is prepared. The substrate 1 may be,for example, a single-crystalline silicon wafer. Hydrogen may be bondedto a top surface of the substrate 1. For example, amino disilane(R¹—Si_(x)H_(y), where “x” is 2, “y” is 5, and “R¹” is the amino group)is supplied as the silicon precursor. In the event that the aminodisilane is supplied to a top surface of the substrate 1, the aminogroup separates the hydrogen of the substrate 1 from the substrate 1. Adisilanyl group of the amino disilane is bonded to a spot from which thehydrogen is separated. At this time, a bond between silicon atoms of thedisilanyl group may be easily broken, and then the silicon atoms may belaterally diffused. The diffused silicon atoms may be adsorbed andbonded to the surface of the substrate 1. Thus, two silicon adsorptionsites may be formed from one amino disilane. As a result, asingle-layered silicon atomic layer 3 may be formed.

Alternatively, as illustrated in FIG. 1B, an oxide layer 5 may bedisposed on the substrate 1. Hydroxyl groups (—OH) may be bonded to atop surface of the oxide layer 5. For example, the amino disilane(R¹—Si_(x)H_(y), where “x” is 2, “y” is 5, and “R¹” is the amino group)is supplied as the silicon precursor. In the event that the aminodisilane is supplied to a top surface of the substrate 1, the aminogroup separates hydrogen from the hydroxyl group. The disilanyl group isadsorbed or bonded to a spot (e.g., an oxygen atom) from the hydrogen isseparated. At this time, a bond between silicon atoms of the disilanylgroup may be easily broken, and then the silicon atoms may be laterallydiffused. The diffused silicon atoms may be adsorbed and bonded to theoxygen atoms of the top surface of the oxide layer 5. Thus, two siliconadsorption sites may be formed from one amino disilane. On the otherhand, if monosilane (SiH₄) is supplied as a silicon precursor, only onesilicon adsorption site may be formed from one silicon precursor.However, the silicon precursor according to the embodiments of theinventive concepts may be supplied to quickly and uniformly thesingle-layered silicon atomic layer 3.

In the present embodiment, the disilane having two silicon atoms isdescribed as an example. However, the inventive concepts are not limitedthereto. If the silicon precursor according to the inventive conceptsincludes a high-grade silane including three or more silicon atoms,three or more silicon adsorption sites may be formed from one siliconprecursor by the same principle as described above.

Hydrogen atoms are bonded to the silicon atom in the silicon atomiclayer 3. However, the hydrogen atoms bonded to the silicon atom may beremoved during a subsequent process of forming a silicon-containinglayer (e.g., a poly-silicon layer, a silicon nitride layer, a siliconoxide layer, or a silicon-germanium layer). In addition, elementsconstituting the silicon-containing layer may be bonded to the siliconatom from which the hydrogen atoms are removed.

A method of forming a layer using the silicon precursor of the inventiveconcepts will be described hereinafter. FIGS. 2A, 2B, and 2C arecross-sectional views illustrating methods of forming a layer accordingto some embodiments of the inventive concepts.

Referring to FIG. 2A, a silicon atomic layer 3 is formed on a substrate1, as described with reference to FIG. 1A. Even though not illustratedin FIG. 2A, the oxide layer 5 may be additionally formed on thesubstrate 1, as described with reference to FIG. 1B. A poly-siliconlayer 7 is formed on the silicon atomic layer 3. The silicon atomiclayer 3 may act as a seed layer for the formation of the poly-siliconlayer 7. In the present embodiment, a silicon precursor supplied for theformation of the silicon atomic layer 3 may be defined as a firstsilicon precursor, and a silicon precursor supplied for the formation ofthe poly-silicon layer 7 may be defined as a second silicon precursor.All kinds of silanes may be used as the second silicon precursorregardless of the number of a silicon atom in the silane. In otherembodiments, the second silicon precursor may include at least one ofmonosilane (SiH₄), disilane (Si₂H₆), or a high-grade silane(Si_(n)H_(2n+2), where “n” is an integral number equal to or greaterthan 3). The second silicon precursor is supplied to separate thehydrogen atom bonded to the silicon atom of the silicon atomic layer 3.At this time, a silicon atom of the second silicon may be bonded to thesilicon atom of the silicon atomic layer 3. Each of the silicon atomiclayer 3 and the poly-silicon layer 7 may be formed by a chemical vapordeposition (CVD) process or a low-pressure CVD process. The siliconatomic layer 3 may be formed in advance within a process apparatus forforming the poly-silicon layer 7. At this time, a process recipe of thesilicon atomic layer 3 may be the same as or similar to that of thepoly-silicon layer 7. A process temperature of the silicon atomic layer3 may be in a range of about 200° C. to about 600° C. In particular, theprocess temperature of the silicon atomic layer 3 may be in a range ofabout 200° C. to about 450° C. If the process temperature is lower than200° C., a deposition rate of the silicon atomic layer 3 may be loweredto deteriorate a seed characteristic of the silicon atomic layer 3. Ifthe process temperature is higher than 450° C., the first siliconprecursor may be decomposed to deteriorate the seed characteristic ofthe silicon atomic layer 3.

During the formation of the poly-silicon layer 7, at least one of GroupIII elements, Group V elements, or carbon may be supplied to dope thepoly-silicon layer 7.

Alternatively, referring to FIG. 2B, a silicon atomic layer 3corresponding to the single-layered silicon atomic layer of FIG. 1A isformed on a substrate 1. Even though not illustrated in FIG. 2B, theoxide layer 5 of FIG. 1B may be additionally formed on the substrate 1.A non-silicon layer 9 corresponding to a single-layered atomic layer isformed on the silicon atomic layer 3. The non-silicon layer 9 may beformed by supplying a precursor including at least one element selectedfrom a group consisting of oxygen, nitrogen, or germanium. The elementmay be bonded to the silicon of the silicon atomic layer 3. At thistime, the hydrogen bonded to the silicon may be removed. The siliconatomic layer 3 and the non-silicon layer 9 may be alternately andrepeatedly formed. Thus, a silicon-containing layer 11 may be formed.The silicon-containing layer 11 may be a silicon oxide layer, a siliconnitride layer, or a silicon-germanium layer. The silicon precursor ofthe inventive concepts may be used as a silicon source for forming thesilicon-containing layer 11. The process of forming thesilicon-containing layer 11 may be a plasma-enhanced CVD (PECVD) processor an atomic layer deposition (ALD) process. A process temperature ofthe PECVD process may be in a range of a room temperature to about 450°C. A process temperature of the ALD process may be in a range of about100° C. to about 450° C. If the process temperature of the ALD processis lower than 100° C., a deposition rate of the silicon atomic layer 3may be low. If the process temperature of the ALD process is higher than450° C., the silicon precursor may be decomposed to deteriorate an ALDcharacteristic.

In still other embodiments, referring to FIG. 2C, a silicon atomic layer3 corresponding to the single-layered silicon atomic layer of FIG. 1A isformed on a substrate 1. Even though not illustrated in FIG. 2C, theoxide layer 5 of FIG. 1B may be additionally formed on the substrate 1.A silicon-containing layer 13 is formed on the silicon atomic layer 3.The silicon-containing layer 13 may be a silicon oxide layer, a siliconnitride layer, or a silicon-germanium layer. Any silicon precursor maybe used when the silicon-containing layer 13 is formed. A morphology orstep coverage characteristic of the silicon-containing layer 13 may beimproved by the existence of the silicon atomic layer 3. The siliconatomic layer 3 may function as a wetting layer.

[First Experimental Example]

Two samples were prepared in the present experimental example. Asingle-layered silicon atomic layer (or a seed layer) was formed usingthe silicon precursor of the inventive concepts on a bare wafer, and apoly-silicon layer was then deposited to prepare a sample according tothe inventive concepts. A single-layered silicon atomic layer was formedusing a silicon precursor of a comparison example on a bare wafer, and apoly-silicon was then deposited to prepare a sample according to thecomparison example. A surface roughness of each of the depositedpoly-silicon layers of the samples was measured. The surface roughnesswas measured according to a thickness of each of the depositedpoly-silicon layers. Dialkylaminodisilane was used as the siliconprecursor of the inventive concepts. Diisopropylaminosilane((C₃H₇)₂N—SiH₃) was used as the silicon precursor of the comparisonexample. Monosilane (SiH₄) was supplied when the poly-silicon layer ofeach sample was deposited. The surface roughness was obtained by a rootmean square method.

FIG. 3 is a graph illustrating the result of a first experimentalexample. Referring to FIG. 3, the surface roughness of the sample usingthe silicon precursor of the inventive concepts is smaller than that ofthe second sample using the silicon precursor of the comparison examplein a substantially entire range of the thickness of the poly-siliconlayer. In particular, the surface roughness of the sample of theinventive concepts is very smaller than that of the sample of thecomparison example in the event that the thickness of the poly-siliconlayer is equal to or smaller than about 100 A (more particularly, 50 Å).The surface roughness (or surface morphology) of the sample of theinventive concepts is equal to or smaller than 2 Å. As a result, it isconfirmed that the silicon precursors of the inventive concepts areuniformly adsorbed on a wafer during a seed deposition process to formthe poly-silicon layer having excellent morphology.

[Second Experimental Example]

Three samples were prepared in the present experimental example. Apoly-silicon layer was directly deposited on a bare wafer to prepare asample according to a first comparison example. In other words, a seedlayer was not formed in the sample of the first comparison example. Aseed layer was formed using a silicon precursor of a comparison exampleon a bare wafer, and a poly-silicon layer was then deposited to preparea sample according to a second comparison example. A seed layer wasformed using the silicon precursor of the inventive concepts on a barewafer, and a poly-silicon was then deposited to prepare a sampleaccording to the inventive concepts. A thickness of each poly-siliconlayer according to a position was measured. Dialkylaminodisilane wasused as the silicon precursor of the inventive concepts.Diisopropylaminosilane ((C₃H₇)₂N—SiH₃) was used as the silicon precursorof the second comparison example. Monosilane (SiH₄) was supplied whenthe poly-silicon layers of each sample was deposited.

FIG. 4 is a graph illustrating the result of a second experimentalexample. Referring to FIG. 4, each of the wafers was loaded in avertical furnace to deposit the poly-silicon layer. Since a reaction gasis supplied in the state the wafer is rotated in the vertical furnace,it may be relatively difficult to supply the reaction gas to a center ofthe wafer (e.g., a position of ‘0’ in FIG. 4). Thus, a deposited layermay be thin on the center of the wafer and may become progressivelythicker toward an edge of the wafer (e.g., positions of ‘150’ and ‘−150’in FIG. 4). The poly-silicon layer is entirely thin in the sample of thefirst comparison example not having the seed layer, so it difficult touse the poly-silicon layer of the first comparison example. In addition,a deviation of the thickness of the poly-silicon layer of the firstcomparison is large, and thus, a uniformity of the poly-silicon layer ispoor. In the sample of the second comparison example, the poly-siliconlayer is entirely thick but a uniformity of the poly-silicon accordingto a position is poor. In the sample of the inventive concepts, thepoly-silicon layer has a sufficient thickness. In addition, thepoly-silicon layer according to the inventive concepts has asubstantially uniform thickness. As a result, the silicon precursors ofthe inventive concepts are uniformly adsorbed on the wafer during theseed deposition process, so the poly-silicon layer of the inventiveconcepts has an excellent uniformity.

Even though not illustrated in FIGS. 2A, 2B, and 2C, the substrate 1 mayhave a lower structure in which a recessed region is formed. The siliconatomic layer 3 may conformally cover the uneven lower structure, and thepoly-silicon layer 7 or the silicon-containing layer 11 or 13 formed onthe silicon atomic layer 3 may have improved uniformity and stepcoverage property. The recessed region may be a contact hole or anactive hole for formation of an active pillar of a three-dimensional(3D) NAND flash memory device. In this case, an aspect ratio of therecessed region may be 10:1 or more. In the event that a layer is formedusing the silicon precursor of the inventive concepts in the recessedregion having the high aspect ratio, the layer may have the excellentstep coverage property, uniformity and morphology. The silicon precursorof the inventive concepts increases the number of silicon-hydrogen bondsas compared with the monosilane. Thus, an incubation time may beimproved, and a surface morphology property of the seed layer may be 1 Åor less. As a result, the silicon precursor according to the inventiveconcepts may overcome limitations of a process of forming a thinpoly-silicon layer.

The method of forming the layer according to the inventive concepts maybe applied to semiconductor fabricating processes such as, for example,a fabricating process of a dynamic random access memory (DRAM) device, afabricating process of a 3D NAND flash memory device, and a doublepatterning process. The silicon precursor of the inventive concepts alsohas an excellent adsorption property on a hydrocarbon layer, and thus,the method of forming the layer according to the inventive concepts maybe applied to a semiconductor fabricating process including a chemicalmechanical polishing (CMP) process using an etch selectivity between thehydrocarbon layer and a silicon layer.

FIGS. 5 to 11 are perspective views illustrating a method of fabricatinga semiconductor device according to some embodiments of the inventiveconcepts. A semiconductor device according to the present embodiment maybe a DRAM device.

Referring to FIG. 5, a device isolation layer 23 may be formed in asubstrate 1 to define active regions AR. The substrate 1 may be, forexample, a silicon wafer substrate or a silicon-on-insulator (SOI)substrate. The device isolation layer 23 may be formed using, forexample, a shallow trench isolation (STI) technique. The deviceisolation layer 23 may be formed of at least one of, for example, asilicon oxide layer, a silicon nitride layer, or a silicon oxynitridelayer. Before the formation of the device isolation layer 23, trenchesmay be formed in the substrate 1 and then the silicon atomic layer 3 ofFIG. 1A may be conformally formed using the silicon precursor of theinventive concepts on the substrate 1. The active regions AR may havebar-shapes extending in a first direction D1.

Referring to FIG. 6, first mask patterns (not shown) extending in asecond direction D2 intersecting the first direction D1 may be formed onthe substrate 1, and the device isolation layer 23 and the substrate 1of the active regions AR may be then etched using the first maskpatterns as an etch mask to form first grooves G1. The first maskpatterns (not shown) may have linear shapes. At this time, an etch rateof the device isolation layer 23 may be higher than an etch rate of thesubstrate 1 by controlling an etch recipe. Thus, a bottom surface of thefirst groove G1 may be uneven. A gate insulating layer 25 may be formedon the substrate 1 exposed by the groove 1. The gate insulating layer 25may be formed of, for example, a thermal oxide layer. A conductive layermay be formed in the first groove G1 having the gate insulating layer 25and may be then recessed to form a word line WL. Subsequently, a firstcapping pattern 27 may be formed on the word line WL in the first grooveG1. The first capping pattern 27 may be formed of, for example, asilicon nitride layer and/or a silicon oxynitride layer. The first maskpatterns (not shown) may be removed, and an ion implantation process maybe then performed to form first dopant injection regions 6 s and seconddopant injection regions 6 d in the substrate 1 not covered with thefirst capping pattern 27. The first dopant injection regions 6 s and thesecond dopant injection regions 6 d may be doped with the dopants of thesame conductivity type, e.g., N-type dopants. A depth of the firstdopant injection region 6 s may be different from that of the seconddopant injection region 6 d. A plurality of ion implantation processesmay be performed to form the first and second dopant injection regions 6s and 6 d having the depths different from each other.

Referring to FIG. 7, a first insulating layer 29 may be formed on anentire surface of the substrate 1. The first insulating layer 29 may beformed of at least one of a silicon oxide layer, a silicon nitridelayer, or a silicon oxynitride layer. A second mask pattern (not shown)may be formed on the first insulating layer 29, and the first insulatinglayer 29 may be patterned using the second mask pattern (not shown) asan etch mask to form openings H1 exposing the second dopant injectionregions 6 d. The opening H1 may have a width greater than that of thesecond dopant injection region 6 d. Thus, the opening H1 may expose thedevice isolation layer 23 and the first capping pattern 27 that areadjacent to the second dopant injection region 6 d.

Referring to FIG. 8, the substrate 1, the device isolation layer 23, andthe first capping pattern 27 which are exposed by the openings H1 may beetched using the second mask pattern (not shown) as an etch mask to formbit line node contact holes DH. A bottom surface of the bit line nodecontact hole DH is higher than a bottom surface of the second dopantinjection region 6 d and a bottom surface of the first capping pattern27. The second mask pattern (not shown) is removed after the formationof the bit line node contact hole DH. Thereafter, a conductive layer 31and a second capping layer 33 may be sequentially formed on the firstinsulating layer 29. The conductive layer 31 may fill the bit line nodecontact holes DH.

Referring to FIG. 9, the second capping layer 33 and the conductivelayer 31 may be successively patterned to form a plurality of secondcapping patterns 33 having linear shapes, bit lines BL under the secondcapping patterns 33, and bit line node contacts DC (or bit line nodecontact plugs DC) in the bit line node contact holes DH. Spacers 40 maybe formed to cover sidewalls of the second capping patterns 33,sidewalls of the bit lines BL, and sidewalls of the bit line nodecontacts DC. The bit line BL may extend in a third direction D3intersecting the first and second directions D1 and D2.

Referring to FIG. 10, spaces between the bit lines BL may be filled witha second insulating layer 42. Portions of the second insulating layer42, the first insulating layer 29, the substrate 1, and the deviceisolation layer 23 may be removed to form storage node contact holes BH.A conductive layer may be formed to fill the storage node contact holesBH, and a planarization process may be then performed on the conductivelayer to form storage node contacts BC (or storage node contact plugsBC).

Referring to FIG. 11, lower electrodes BE may be formed to be connectedto the storage node contacts BC, Even though not illustrated in thedrawings, a dielectric layer and an upper electrode may be formed on thelower electrodes BE.

In the present embodiment, the device isolation layer 23, the insulatinglayers 25, 29, and 42, and the capping layers 27 and 33 may be formed ofa silicon oxide layer and/or a silicon nitride layer, and the siliconprecursor of the inventive concepts may be used as silicon sources forthe formation of the layers 23, 25, 29, 42, 27 and 33. In the presentembodiment, the storage node contact BC, the bit line node contact DC,the word line WL, and/or the bit line BL may be formed of a poly-siliconlayer doped with dopants. In this case, a silicon seed layer may beformed using the silicon precursor of the inventive concept for theformation of the poly-silicon layers of the storage node contact BC, thebit line node contact DC, the word line WL, and/or the bit line BL. Inparticular, since the DRAM device according to the present embodimentincludes a buried word line, the trench for the formation of the deviceisolation layer 23 and/or the groove for the formation of the word lineWL may have a high aspect ratio. In addition, the storage node contacthole BH may have a high aspect ratio. Generally, it may be difficult tofill a recessed region having a high aspect ratio with a material layerwithout a void. However, this difficulty may be solved by the siliconprecursor of the inventive concepts.

FIG. 12 is a plan view illustrating a semiconductor device according toother embodiments of the inventive concepts. FIGS. 13 to 17 arecross-sectional views taken along a line A-A′ of FIG. 12 to illustrate amethod of fabricating the semiconductor device of FIG. 12. Asemiconductor device according to the present embodiment may be avertical NAND flash memory device.

Referring to FIGS. 12 and 13, a buffer oxide layer 103 may be formed ona substrate 1. Sacrificial layers 105 and inter-gate insulating layers107 may be alternately and repeatedly formed (or stacked) on the bufferoxide layer 103. The sacrificial layers 105 may be formed of a materialhaving an etch rate different from that of the inter-gate insulatinglayers 107. For example, each of the sacrificial layers 105 may beformed of a silicon nitride layer, and each of the inter-gate insulatinglayers 107 may be formed of a silicon oxide layer. The inter-gateinsulating layers 107, the sacrificial layers 105, and the buffer oxidelayer 103 may be successively patterned to form active holes 109exposing the substrate 1. An aspect ratio of the active hole 109 may be10:1 or more.

Referring to FIGS. 12 and 14, a gate insulating layer 111 and a firstactive layer 113 may be sequentially on an entire surface of thesubstrate 1 having the active holes 109. The gate insulating layer 111and the first active layer 113 may be conformally formed in the activeholes 109. The gate insulating layer 111 may include at least a tunnelinsulating layer and a data storage layer. The tunnel insulating layermay be formed of a silicon oxide layer, and the data storage layer maybe formed of a silicon nitride layer. The gate insulating layer 111 maybe formed using the method of forming the layer according to embodimentsof the inventive concepts. Since silicon precursor of the inventiveconcepts has the adsorption property that is substantially uniform onall of the substrate 1 formed of silicon, the sacrificial layer 105formed of a silicon nitride layer and the inter-gate insulating layer107 formed of a silicon oxide layer, the gate insulating layer 111 mayhave excellent step coverage property, morphology and uniformity. Thegate insulating layer 111 and the first active layer 113 may beanisotropically etched to form a gate insulating layer 111 and a firstactive layer 113 having spacer-shapes and to expose the substrate 1 of abottom surface of the active hole 109. The first active layer 113 may beformed of a poly-silicon layer. In this case, step coverage, morphologyand uniformity properties of the first active layer 113 are veryimportant. If these properties of the first active layer 113 are poor, aportion of the gate insulating layer 111 may be exposed and damagedduring the anisotropic etching process. Thus, operating errors of adevice may occur. However, the first active layer 113 is formed usingthe method of forming the layer according to embodiments of theinventive concepts, so these properties of the first active layer 113are excellent. Thus, the problems such as the operating errors may beprevented. Subsequently, a second active layer 115 may be conformallyformed, and a first filling insulation layer 117 may be formed to fillthe active hole 109. The second active layer 115 may be formed of apoly-silicon layer using the method of forming the layer according toembodiments of the inventive concepts. Thereafter, a planarizationprocess may be performed to form an active pillar AP. The active pillarAP includes the first active layer 113 having the spacer-shape and thesecond active layer 115 planarized by the planarization process. Thegate insulating layer 113, the active pillar AP, and the first fillinginsulation layer 117 may remain in the active hole 109 after theplanarization process is performed. The first filling insulation layer117 may be formed of a silicon oxide layer.

Referring to FIGS. 12 and 15, the inter-gate insulating layers 107, thesacrificial layers 105 and the buffer oxide layer 103 may besuccessively patterned to grooves 119 exposing the substrate 1. Thegrooves 119 are spaced apart from the active holes 109. An ionimplantation process may be performed to form common source lines CSL inthe substrate 1 exposed by the grooves 119, and a drain region D may beformed in a top end portion of the active pillar AP.

Referring to FIGS. 12 and 16, an isotropic etching process may beperformed to partially remove the sacrificial layers 105 through thegrooves 119. During the isotropic etching process, an etchant may beprovided to sidewall portions of the sacrificial layers 105 exposed bythe grooves 119. At this time, a process time of the isotropic etchingprocess may be controlled to the isotropic etching process before entireportions of the sacrificial layers 105 are removed. Thus, portions ofthe sacrificial layers 105, which are far away from the groove 119, maynot be removed, so sacrificial patterns 105 p may remain. Thesacrificial patterns 105 p may be formed in a center region of a regionbetween the grooves 119 adjacent to each other. In addition, sidewallsof the sacrificial patterns 105 p may concavely formed by the isotropicetching process. This is because the etchant may more easily approach acentral portion of the sidewall of the sacrificial pattern 105 p thanedge portions (i.e., top and bottom portions) of the sidewall of thesacrificial pattern 105 p. Thus, the central portion of the sidewall ofthe sacrificial pattern 105 p may be more etched. By the isotropicetching process, the sacrificial layers 105 may be partially etched toform empty spaces 119 a.

Referring to FIGS. 12 and 17, a high-k dielectric layer 122 may beconformally formed on the substrate 1. Subsequently, a conductive layermay be formed to fill the empty spaces 119 a. At this time, theconductive layer may also be formed in the trenches 119. The conductivelayer in the trenches 119 may be removed to form lower selection linesLSL, word lines WL, and upper selection lines USL. Thereafter, secondfilling insulation patterns 120 may be formed in the grooves 119.Subsequently, bit lines BL may be formed to be connected to the drainregions D.

FIG. 18 is a schematic block diagram illustrating an electronic deviceincluding a semiconductor device according to embodiments of theinventive concepts.

Referring to FIG. 18, an electronic device 1300 according to embodimentsof the inventive concepts may be a personal digital assistant (PDA), alaptop computer, a portable computer, a web tablet, a wireless phone, amobile phone, a digital music player, a cable/wireless electronicdevice, or a complex electronic device including at least two thereof.The electronic device 1300 may include a controller 1310, aninput/output (I/O) unit 1320 (e.g., a keypad, a keyboard, and/or adisplay), a memory device 1330 and a wireless interface unit 1340 thatcommunicate with each other through a data bus 1350. For example, thecontroller 1310 may include at least one of a microprocessor, a digitalsignal processor, a microcontroller, or other logic devices having asimilar function to any one thereof. The memory device 1330 may storedata and/or commands executed by the controller 1310. The memory device1330 may include at least one of semiconductor devices according toembodiments of the inventive concepts. The electronic device 1300 mayuse the wireless interface unit 1340 to transmit electrical data to awireless communication network communicating with a radio frequency (RF)signal or to receive electrical data from a communication network. Forexample, the wireless interface unit 1340 may include an antenna or awireless transceiver. The electronic device 1300 may be used in acommunication interface protocol such as a communication system such asCDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000, Wi-Fi, Muni Wi-Fi, Bluetooth,DECT, Wireless USB, Flash-OFDM, IEEE 802.20, GPRS, iBurst, WiBro, WiMAX,WiMAX-Advanced, UMTS-TDD, HSPA, EVDO, LTE-Advanced, or MMDS.

FIG. 19 is a schematic block diagram illustrating a memory systemincluding a semiconductor device according to embodiments of theinventive concepts.

Referring to FIG. 19, the semiconductor devices according to embodimentsof the inventive concepts may be used to realize a memory system. Amemory card 1400 may include a memory device 1410 and a memorycontroller 1420 that store massive data. The memory controller 1420 mayread data from/store data into the memory device 1410 in response toread/write request of a host 1430. The memory controller 1420 may makean address mapping table for mapping an address provided from the host1430 (e.g., a mobile device or a computer system) into a physicaladdress of the memory device 1410. The memory device 1410 may include atleast one of the semiconductor devices according to the aboveembodiments of the inventive concepts.

According to some embodiments of the inventive concepts, the siliconprecursor includes a silane group including two or more silicon atoms.The silicon precursor has a high and uniform adsorption property onsurfaces of layers (e.g., a silicon layer, an oxide layer, and a nitridelayer) that are mainly used when semiconductor devices are fabricated.Thus, the layer having an excellent seed property may be provided. Inaddition, the silicon precursor of the inventive concepts increases thenumber of silicon-hydrogen bonds as compared with the monosilane. Thus,an incubation time may be improved, and a surface morphology property ofthe seed layer may be 1 Å or less. As a result, the silicon precursoraccording to the inventive concepts may overcome limitations of aprocess of forming a thin poly-silicon layer.

According to other embodiments of the inventive concepts, the layer maybe formed using the silicon precursor, so the step coverage property ofthe layer may be improved.

According to still embodiments of the inventive concepts, thesemiconductor device may be fabricated using the silicon precursor, andthus, it is possible to prevent a void from being formed in the contacthole or the active hole. As a result, reliability of the semiconductordevice may be improved.

While the inventive concepts have been described with reference toexample embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the inventive concepts. Therefore, itshould be understood that the above embodiments are not limiting, butillustrative. Thus, the scopes of the inventive concepts are to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

What is claimed is:
 1. A method of forming a layer, the methodcomprising: providing a silicon precursor having a chemical formula ofR¹—Si_(x)H_(y), on a substrate to form a single-layered silicon atomiclayer, wherein x is an integral number equal to or greater than 2, ysatisfies an equation having a formula of y=2x+1, and R¹ includes atleast one of an amino group, an alkyl group, a cyclopentadienyl (C₅H₅)group, or a halogen.
 2. The method of claim 1, further comprising:forming a silicon nitride layer, a silicon oxide layer, or asilicon-germanium layer on the single-layered silicon atomic layer. 3.The method of claim 1, further comprising: forming a poly-silicon layeron the single-layered silicon atomic layer by providing at least one ofmonosilane (SiH₄), disilane (Si₂H₆), or a high-grade silane having achemical formula of Si_(n)H_(2n+2), wherein n is an integral numberequal to or greater than
 3. 4. The method of claim 3, wherein formingthe poly-silicon layer further comprises: doping the poly-silicon layerby providing at least one of Group III elements, Group V elements, orcarbon.
 5. The method of claim 1, further comprising: forming anon-silicon atomic layer on the single-layered silicon atomic layer,wherein forming the single-layered silicon atomic layer and forming thenon-silicon atomic layer are alternately and repeatedly performed, andwherein the non-silicon atomic layer is formed by providing a gasincluding oxygen, nitrogen, or germanium.
 6. The method of claim 1,wherein R¹ has the following chemical formula 1,

wherein each of R² and R³ independently include at least one of a methylgroup, an ethyl group, a propyl group, an isopropyl group, a butylgroup, or a tert-butyl group.
 7. The method of claim 1, wherein thesilicon precursor is diisopropylaminodisilane (((CH₃)₂CH)₂N—SiH₂SiH₃).8. The method of claim 1, wherein the substrate includes an oxide layerformed thereon, and wherein the silicon precursor is provided on theoxide layer.
 9. A method of fabricating a semiconductor device, themethod comprising: providing a silicon precursor having a chemicalformula of R¹—Si_(x)H_(y) on a substrate to form a single-layeredsilicon atomic layer, wherein x is an integral number equal to orgreater than 2, y satisfies an equation having a formula of y=2x+1, andR¹ includes at least one of an amino group, an alkyl group, acyclopentadienyl (C₅H₅) group, or a halogen.
 10. The method of claim 9,further comprising: forming a lower structure including a recessedregion on the substrate before the formation of the single-layeredsilicon atomic layer, wherein the single-layered silicon atomic layer isformed to conformally cover the lower structure.
 11. The method of claim10, wherein the recessed region is a contact hole, and wherein formingthe lower structure comprises: forming an interlayer insulating layercovering the substrate; and patterning the interlayer insulating layerto form the contact hole.
 12. The method of claim 11, furthercomprising: after the formation of the single-layered silicon atomiclayer, forming a poly-silicon layer filling the contact hole on thesingle-layered silicon atomic layer by providing at least one ofmonosilane (SiH₄), disilane (Si₂H₆), or a high-grade silane having achemical formula of Si_(n)H_(2n+2), wherein n is an integral numberequal to or greater than
 3. 13. The method of claim 12, furthercomprising: forming a contact plug including a portion of thepoly-silicon layer in the contact hole; and forming a data storageelement electrically connected to the contact plug.
 14. The method ofclaim 10, wherein the recessed region is an active hole, and whereinforming the lower structure comprises: alternately and repeatedlystacking sacrificial layers and inter-gate insulating layers on thesubstrate; and successively patterning the inter-gate insulating layersand the sacrificial layers to form the active hole exposing thesubstrate.
 15. The method of claim 14, further comprising: forming anactive pillar covering a sidewall of the active hole after the formationof the single-layered silicon atomic layer, the active pillar having acup-shape; and replacing the sacrificial layers with a conductive layer.16. The method of claim 15, wherein forming the active pillar comprises:conformally forming a poly-silicon layer on the single-layered siliconatomic layer by providing at least one of monosilane (SiH₄), disilane(Si₂H₆), or a high-grade silane having a chemical formula ofSi_(n)H_(2n+2), wherein n is an integral number equal to or greater than3, the poly-silicon layer covering the sidewall of the active hole. 17.The method of claim 9, wherein R¹ has the following chemical formula 1,

wherein each of R² and R³ independently include at least one of a methylgroup, an ethyl group, a propyl group, an isopropyl group, or a butylgroup.
 18. The method of claim 10, wherein R¹ has the following chemicalformula 1,

wherein each of R² and R³ independently include at least one of a methylgroup, an ethyl group, a propyl group, an isopropyl group, or a butylgroup.
 19. The method of claim 9, wherein the silicon precursor isdiisopropylaminodisilane (((CH₃)₂CH)₂N—SiH₂SiH₃).
 20. The method ofclaim 9, wherein the substrate includes an oxide layer formed thereon,and wherein the silicon precursor is provided on the oxide layer.